1. Technical Field
The embodiments herein generally relate to test vector generation systems and methods and more particularly relates to automated generation of unique test vectors for verification of integrated circuit chip configuration.
2. Description of the Related Art
Currently for the chip vendor industry, it is unavoidable to perform various tests on integrated circuit chips with different specifications to verify whether the operation of the design is correct or not. Therefore, the quality control and test for several products has become a significant issue in the chip vending industry. The chip vending companies are facing an unprecedented challenge of balancing the design realization time, cost and the product market life of the integrated circuit (IC) chips. Further in the current scenario, the system on chip (SoC) has a market life and a design realization time which is considerably negligible.
In the existing techniques, the process of IC design verification is done manually using several automation techniques such as a constraint random verification. The constraints that specify the state space of different variables and the inter-relationship between the variables need to be written manually and then the constraints need to be passed through various constraint solver tools to generate legal random numbers for a set of variables. The overall process requires user intervention at regular time intervals and also consumes a lot of time. Further the existing techniques do not provide for automatic generation of aligned constraints and coverage objects to monitor and report the quality of the vectors generated. In the existing technique, the user assumes that the chip has just one verification state space, but in reality the chip could contain several high level configurations which could affect the quantity and state space of vectors to a large extent.
Generally large ASIC/SOCs requires several million test vectors for coverage closure due to its huge functionality and multiple application scenarios. However the existing constrained random verification technology includes various limitations such as running several regression of constraint solver to cover the entire state space. Also within a regression, the tests need to be divided and performed across the different machines in the system pool.
Hence there is a need for a method and system for automatically generating a unique set of vector for design verification of a multi-configuration chip. There also exists a need for a system and method to prevent generation of repeated test vectors across machines in a single regression. Further there exists a need for a system and method to prevent generation of repeated test vectors across various regressions.
The above mentioned shortcomings, disadvantages and problems are addressed herein and which will be understood by reading and studying the following specification.